EP3SE80F780I4N Datasheet, PDF (324/341 Pages) Altera Corporation – Chapter Revision Dates

1–314
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–156 and Table 1–157 list the regional clock timing parameters for EP3SL110
devices.
Table 1–156. EP3SL110 Column Pin Regional Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
1.689
1.687
2.360 2.600 2.924 2.836 3.241 2.600 2.924 2.836 3.241 ns
1.689
1.687
2.360 2.600 2.924 2.836 3.241 2.600 2.924 2.836 3.241 ns
-0.036
-0.038 -0.262 -0.317 -0.278 -0.239 -0.020 -0.317 -0.278 -0.239 -0.020 ns
-0.036
-0.038 -0.262 -0.317 -0.278 -0.239 -0.020 -0.317 -0.278 -0.239 -0.020 ns
Table 1–157. EP3SL110 Row Pin Regional Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
Industrial Commercial
1.684
1.602
0.008
-0.074
1.792
1.701
0.071
-0.020
C2
V_CCL=
1.1 V
2.440
2.298
-0.189
-0.334
C3
V_CCL=
1.1 V
2.644
2.481
-0.276
-0.439
C4
V_CCL=
1.1 V
2.985
2.804
-0.218
-0.399
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.879 3.044
2.708 2.885
-0.188 -0.214
-0.359 -0.373
I3
V_CCL=
1.1 V
2.720
2.550
-0.209
-0.379
I4
V_CCL=
1.1 V
3.044
2.855
-0.174
-0.363
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.938 3.083
2.759 2.924
-0.141 -0.263
-0.320 -0.422
Units
ns
ns
ns
ns
Table 1–158 and Table 1–159 list the periphery clock timing parameters for EP3SL110
devices.
.
Table 1–158. EP3SL110 Column Pin Periphery Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
Industrial
1.541
1.541
-0.029
-0.029
Commercial
1.538
1.538
-0.031
-0.031
C2
V_CCL=
1.1 V
2.257
2.257
-0.253
-0.253
C3
V_CCL=
1.1 V
2.539
2.539
-0.310
-0.310
C4
V_CCL=
1.1 V
2.931
2.931
-0.276
-0.276
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.810 3.345
2.810 3.345
-0.222 -0.020
-0.222 -0.020
I3
V_CCL=
1.1 V
2.539
2.539
-0.310
-0.310
I4
V_CCL=
1.1 V
2.931
2.931
-0.276
-0.276
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.810 3.345
2.810 3.345
-0.222 -0.020
-0.222 -0.020
Units
ns
ns
ns
ns
Table 1–159. EP3SL110 Row Pin Periphery Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
Industrial Commercial
1.430
1.348
0.015
-0.067
1.503
1.412
0.072
-0.019
C2
V_CCL=
1.1 V
2.156
2.011
-0.188
-0.333
C3
V_CCL=
1.1 V
2.416
2.253
-0.267
-0.430
C4
V_CCL=
1.1 V
2.783
2.602
-0.219
-0.400
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.665 2.926
2.494 2.767
-0.180 -0.214
-0.351 -0.373
I3
V_CCL=
1.1 V
2.465
2.295
-0.206
-0.376
I4
V_CCL=
1.1 V
2.828
2.639
-0.170
-0.359
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
2.711 2.951
2.532 2.792
-0.133 -0.263
-0.312 -0.422
Units
ns
ns
ns
ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation