EP3SE80F780I4N Datasheet, PDF (238/341 Pages) Altera Corporation – Chapter Revision Dates

1–228
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–109 and Table 1–110 list the EP3SE50 regional clock (RCLK) adder values that
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–109 lists the EP3SE50 column pin delay adders when using the regional clock
in Stratix III devices.
Table 1–109. EP3SE50 Column Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output
adder
Fast Model
Industrial Commercial
0.152
-0.001
-0.116
0.164
-0.001
-0.119
1.647
1.684
C2
C3
V_CCL=
1.1 V
V_CCL=
1.1 V
0.22 0.237
-0.003 -0.004
-0.134 -0.136
2.61 2.926
C4
V_CCL=
1.1 V
0.25
-0.004
-0.17
3.238
C4L
V_CCL=
1.1 V
0.244
-0.004
-0.171
V_CCL=
0.9 V
0.31
-0.006
-0.249
3.084 3.298
I3
V_CCL=
1.1 V
0.24
-0.003
-0.131
2.943
I4
V_CCL=
1.1 V
0.254
-0.004
-0.13
3.254
I4L
V_CCL=
1.1 V
0.246
-0.004
-0.13
V_CCL=
0.9 V
0.312
-0.006
-0.216
3.098 3.374
Units
ns
ns
ns
ns
Table 1–110 lists the EP3SE50 row pin delay adders when using the regional clock in
Stratix III devices.
Table 1–110. EP3SE50 Row Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.113
0.13
-0.116
-0.137
0.125
0.14
-0.129
-0.143
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
0.182 0.197 0.212 0.205 0.274 0.201 0.215 0.21 0.275 ns
0.213 0.241 0.267 0.255 0.385 0.244 0.27 0.256 0.386 ns
-0.186 -0.202 -0.218 -0.209 -0.28 -0.206 -0.221 -0.214 -0.283 ns
-0.193 -0.214 -0.236 -0.225 -0.295 -0.215 -0.237 -0.226 -0.297 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation