EP3SE80F780I4N Datasheet, PDF (25/341 Pages) Altera Corporation – Chapter Revision Dates

Table 1–20. PLL Specifications for Stratix III Devices (Part 2 of 3)
C2
C3, I3
C4, I4
C4L, I4L
Symbol
f_CLBW
t_{PLL_PSERR}
t_ARESET
t_INCCJ (3), (4)
t_{OUTPJ_DC} (5)
t (5) _{OUTCCJ_DC}
t_{OUTPJ_IO} (5), (8)
Parameter
PLL closed-loop low bandwidth
PLL closed-loop medium
bandwidth
PLL closed-loop high bandwidth
(6)
Accuracy of PLL phase shift
Minimum pulse width on areset
signal
Input clock cycle to cycle jitter
(F_REF  100 MHz)
Input clock cycle to cycle jitter
(F_REF < 100 MHz)
Period Jitter for dedicated clock
output (F_OUT 100 MHz)
Period Jitter for dedicated clock
output (F_OUT < 100 MHz)
Cycle to Cycle Jitter for dedicated
clock output
(F_OUT 100 MHz)
Cycle to Cycle Jitter for dedicated
clock output
(F_OUT < 100 MHz)
Period Jitter for clock output on
regular IO (F_OUT  100 MHz)
Period Jitter for clock output on
regular IO (F_OUT < 100 MHz)
V_CCL = 1.1 V
V_CCL = 1.1 V
V_CCL = 1.1 V
V_CCL = 1.1 V
V_CCL = 0.9 V
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
— 0.3 — — 0.3 — — 0.3 — — 0.3 — — 0.3 — MHz
— 1.5 — — 1.5 — — 1.5 — — 1.5 — — 1.5 — MHz
— 4 — — 4 — — 4 — — 4 — — 4 — MHz
— — ±50 — — ±50 — — ±50 — — ±50 — — ±50 ps
10 — — 10 — — 10 — — 10 — — 10 — — ns
— — 0.15 — — 0.15 — — 0.15 — — 0.15 — — 0.1 UI (p-p)
— — ±750 — — ±750 — — ±750 — — ±750 — — ±500 ps (p-p)
— — 175 — — 175 — — 175 — — 175 — — 225 ps (p-p)
—
— 17.5 —
— 17.5 —
— 17.5 —
— 17.5 —
—
22.5
mUI
(p-p)
— — 175 — — 175 — — 175 — — 175 — — 225 ps (p-p)
—
— 17.5 —
— 17.5 —
— 17.5 —
— 17.5 —
—
22.5
mUI
(p-p)
— — 600 — — 600 — — 600 — — 600 — — 750 ps (p-p)
—
—
60
—
—
60
—
—
60
—
—
60
—
—
75
mUI
(p-p)