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EP3SE80F780I4N Datasheet, PDF (169/341 Pages) Altera Corporation – Chapter Revision Dates
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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–159
Table 1–84 lists the EP3SL200 row pins output timing parameters for single-ended
I/O standards.
Table 1–84. EP3SL200 Row Pins Output Timing Parameters (Part 1 of 4)
I/O
Standard
Clock
3.3-V
LVTTL
4mA
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
GCLK
PLL
tco
GCLK tco
12mA
GCLK
PLL
tco
4mA
3.3-V
LVCMOS
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
GCLK
PLL
tco
3.0-V
LVTTL
4mA
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
GCLK
PLL
tco
GCLK tco
12mA
GCLK
PLL
tco
3.0-V
LVCMOS
GCLK tco
4mA
GCLK
PLL
tco
GCLK tco
8mA
GCLK
PLL
tco
4mA
GCLK tco
GCLK
PLL
tco
2.5 V
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
12mA
GCLK
PLL
tco
Fast Model
Industrial Commercial
C2
VCCL=
1.1 V
C3
VCCL=
1.1 V
C4
VCCL=
1.1 V
C4L
VCCL= VCCL=
1.1 V 0.9 V
I3
VCCL=
1.1 V
I4
VCCL=
1.1 V
I4L
VCCL= VCCL=
1.1 V 0.9 V
Units
3.639
3.902 5.663 5.916 6.397 6.238 6.709 6.053 6.634 6.238 6.709 ns
1.551
1.768 2.210 2.317 2.505 2.518 2.444 2.409 2.649 2.518 2.444 ns
3.548
3.813 5.533 5.778 6.283 6.124 6.565 5.912 6.485 6.124 6.565 ns
1.468
1.663 2.080 2.179 2.361 2.374 2.300 2.268 2.500 2.374 2.300 ns
3.469
3.724 5.414 5.655 6.187 6.028 6.437 5.785 6.353 6.028 6.437 ns
1.389
1.560 1.961 2.056 2.233 2.246 2.172 2.147 2.368 2.246 2.172 ns
3.649
3.906 5.671 5.921 6.406 6.247 6.714 6.059 6.639 6.247 6.714 ns
1.561
1.772 2.218 2.322 2.510 2.523 2.449 2.415 2.654 2.523 2.449 ns
3.473
3.728 5.420 5.661 6.197 6.038 6.443 5.794 6.360 6.038 6.443 ns
1.393
1.564 1.967 2.062 2.239 2.252 2.178 2.159 2.375 2.252 2.178 ns
3.593
3.848 5.615 5.869 6.363 6.204 6.666 6.010 6.592 6.204 6.666 ns
1.505
1.714 2.162 2.270 2.462 2.475 2.401 2.366 2.607 2.475 2.401 ns
3.474
3.733 5.463 5.710 6.218 6.059 6.502 5.848 6.428 6.059 6.502 ns
1.394
1.587 2.010 2.111 2.298 2.311 2.237 2.204 2.443 2.311 2.237 ns
3.437
3.695 5.395 5.627 6.148 5.989 6.414 5.762 6.335 5.989 6.414 ns
1.357
1.536 1.928 2.028 2.210 2.223 2.149 2.118 2.350 2.223 2.149 ns
3.507
3.767 5.510 5.762 6.254 6.095 6.555 5.902 6.481 6.095 6.555 ns
1.419
1.633 2.057 2.163 2.351 2.364 2.290 2.258 2.496 2.364 2.290 ns
3.424
3.679 5.368 5.588 6.120 5.961 6.375 5.722 6.295 5.961 6.375 ns
1.344
1.515 1.893 1.989 2.171 2.184 2.110 2.087 2.310 2.184 2.110 ns
3.619
3.884 5.748 6.023 6.508 6.349 6.838 6.170 6.771 6.349 6.838 ns
1.531
1.750 2.295 2.424 2.634 2.647 2.573 2.526 2.786 2.647 2.573 ns
3.516
3.785 5.593 5.860 6.366 6.207 6.668 6.003 6.597 6.207 6.668 ns
1.436
1.651 2.140 2.261 2.464 2.477 2.403 2.359 2.612 2.477 2.403 ns
3.463
3.735 5.492 5.741 6.275 6.116 6.542 5.880 6.467 6.116 6.542 ns
1.379
1.575 2.029 2.142 2.338 2.351 2.277 2.236 2.482 2.351 2.277 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2
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