Z80181 Datasheet, PDF (8/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
SCC SIGNALS (Continued)
Pin Name
TxD
Pin Number
54
Input/Output, Tri-State
Out, Active 1
/DTR//REQ 55
Out, Active 0
/RTS
56
Out, Active 0
/CTS
57
In, Active 0
/DCD
58
In, Active 0
Z80181
SMART ACCESS CONTROLLER SAC^™
Function
Transmit Data. This Output signal transmits serial data at
standard TTL level.
Data Terminal Ready/Request. This output follows the
state programmed into the DTR bit. It can also be used as
general-purpose output or as Request line for a DMA
controller.
Request To Send. When the RTS bit in Write Register 5 is
set, the /RTS signal goes low. When the RTS bit is reset in
Asynchronous mode and auto enable is on, the signal
goes high after the transmitter is empty. In synchronous
mode or in Asynchronous mode, with Auto Enable off, the
/RTS pin follows the state of the RTS bit. This pin can be
used as a general-purpose output.
Clear To Send. If this pin is programmed as auto enable,
a “0” on the input enables the transmitter. If not pro-
grammed as Auto Enable, it may be used as a general-
purpose input. This input is Schmitt-trigger buffered to
accommodate inputs with slow rise times. The SCC de-
tects pulses on this input and can interrupt the CPU on both
logic level transitions.
Data Carrier Detect. This pin functions as receiver enable
if it is programmed for auto enable. Otherwise, it may be
used as a general-purpose input. This input is Schmitt-
trigger buffered to accommodate slow rise-time inputs.
The SCC detects pulses on this input and can interrupt the
CPU on both logic level transitions.
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DS971800500