Z80181 Datasheet, PDF (58/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
AC CHARACTERISTICS (Continued)
Z180 MPU Timing
Z80181
SMART ACCESS CONTROLLER SAC^™
CSI/O Clock
Transmit Data
(Internal Clock)
Transmit Data
(External Clock)
Receive Data
(Internal Clock)
Receive Data
(External Clock)
55
56
11 tcyc
57
58
11.5 tcyc
16.5 tcyc
55
56
11 tcyc
57
58
11.5 tcyc
16.5 tcyc
59
60
59
60
Figure 68. CSI/O Receive/Transmit Timing
No Symbol
1
tcyc
2
tCHW
3
tCLW
4
tcf
5
tcr
6
tAD
7
tAS
8
tMED1
9
tRDD1
10 tM1D1
Table A. Z180 CPU & 180 Peripherals Timing
Parameter
Z8018110
Min
Max
Unit
Clock Cycle Time
Clock Pulse Width (High)
Clock Pulse Width (Low)
Clock Fall Time
100
2000
ns
40
ns
40
ns
10
ns
Clock Rise Time
Address Valid from Clock Rise
Address Valid to /MREQ, /IORQ Fall
Clock Fall to /MREQ Fall Delay
Clock Fall to /RD Fall (/IOC=1)
Clock Rise to /RD Fall (/IOC=0)
Clock Rise to /M1 Fall Delay
10
ns
70
ns
10
ns
50
ns
50
ns
55
ns
60
ns
2-58
DS971800500