Z80181 Datasheet, PDF (38/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
SCC REGISTERS (Continued)
Write Register 3
D7 D6 D5 D4 D3 D2 D1 D0
0 0 Rx 5 Bits/Character
0 1 Rx 7 Bits/Character
1 0 Rx 6 Bits/Character
1 1 Rx 8 Bits/Character
(d)
Z80181
SMART ACCESS CONTROLLER SAC^™
Rx Enable
Sync Character Load Inhibit
Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Mode
Auto Enables
Write Register 4
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 5
D7 D6 D5 D4 D3 D2 D1 D0
Parity Enable
Parity EVEN//ODD
0 0 Sync Modes Enable
0 1 1 Stop Bit/Character
1 0 1 1/2 Stop Bits/Character
1 1 2 Stop Bits/Character
0 0 8-Bit Sync Character
0 1 16-Bit Sync Character
1 0 SDLC Mode (01111110 Flag)
1 1 External Sync Mode
0 0 X1 Clock Mode
0 1 X16 Clock Mode
1 0 X32 Clock Mode
1 1 X64 Clock Mode
Tx CRC Enable
RTS
/SDLC/CRC-16
Tx Enable
Send Break
0 0 Tx 5 Bits(Or Less)/Character
0 1 Tx 7 Bits/Character
1 0 Tx 6 Bits/Character
1 1 Tx 8 Bits/Character
DTR
(f)
(e)
Figure 50. Write Register Bit Functions (Continued)
2-38
DS971800500