Z80181 Datasheet, PDF (37/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Write Register 0 (non-multiplexed bus mode)
D7 D6 D5 D4 D3 D2 D1 D0
Z80181
SMART ACCESS CONTROLLER SAC^™
Write Register 1
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 Register 0
0 0 1 Register 1
0 1 0 Register 2
0 1 1 Register 3
1 0 0 Register 4
1 0 1 Register 5
1 1 0 Register 6
1 1 1 Register 7
0 0 0 Register 8
0 0 1 Register 9
0 1 0 Register 10
0 1 1 Register 11
1 0 0 Register 12
*
1 0 1 Register 13
1 1 0 Register 14
1 1 1 Register 15
0 0 0 Null Code
0 0 1 Point High
0 1 0 Reset Ext/Status Interrupts
0 1 1 Send Abort (SDLC)
1 0 0 Enable Int on Next Rx Character
1 0 1 Reset Tx Int Pending
1 1 0 Error Reset
1 1 1 Reset Highest IUS
0 0 Null Code
0 1 Reset Rx CRC Checker
1 0 Reset Tx CRC Generator
1 1 Reset Tx Underrun/EOM Latch
* ^{With Point High Command}
(a)
Ext Int Enable
Tx Int Enable
Parity is Special
Condition
0 0 Rx Int Disable
0 1 Rx Int On First Character or
Special Condition
1 0 Int On All Rx Characters or
Special Condition
1 1 Rx Int On Special Condition Only
WAIT/DMA Request
On Receive//Transmit
/WAIT/DMA Request
Function
WAIT/DMA Request
Enable
(b)
Write Register 2
D7 D6 D5 D4 D3 D2 D1 D0
V0
V1
V2
V3
Interrupt
V4
Vector
V5
V6
V7
(c)
Figure 50. Write Register Bit Functions
DS971800500
2-37