Z80181 Datasheet, PDF (21/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Z80181
SMART ACCESS CONTROLLER SAC^™
STAT0
Bit RDRF OVRN PE
Upon Reset
0
0
0
R/W R
R
R
Addr 04h
FE RIE /DCD0 TDRE TIE
0
0
†
††
0
R R/W R
R R/W
Transmit Interrupt Enable
Transmit Data Register
Empty
Data Carrier Detect
Receive Interrupt Enable
Framing Error
Parity Error
Over Run Error
Receive Data Register Full
† /DCD0 - Depending on the condition of /DCD0 Pin.
†† /CTS0 Pin TDRE
L
1
H
0
Figure 11. ASCI Status Register
STAT1
Bit RDRF OVRN PE
Upon Reset
0
0
0
R/W R
R
R
Addr 05h
FE RIE CTS1E TDRE TIE
0
0
0
1
0
R R/W R/W R R/W
Transmit Interrupt Enable
Transmit Data Register
Empty
/CTS1 Enable
Receive Interrupt Enable
Framing Error
Parity Error
Over Run Error
Receive Data Register Full
Figure 12. ASCI Status Register (Ch. 1)
DS971800500
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