Z80181 Datasheet, PDF (40/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
SCC REGISTERS (Continued)
Write Register 9
D7 D6 D5 D4 D3 D2 D1 D0
Z80181
SMART ACCESS CONTROLLER SAC^™
Write Register 11
D7 D6 D5 D4 D3 D2 D1 D0
0 0 No Reset
0 1 Reserved
1 0 Channel Reset A
1 1 Force Hardware Reset
(i)
VIS
NV
DLC
MIE
Status High//Status Low
0
0 0 /TRxC Out - Xtal Output
0 1 /TRxC Out - Transmit Clock
1 0 /TRxC Out - BR Generator Output
1 1 /TRxC Out - DPLL Output
/TRxC O/I
0 0 Transmit Clock - /RTxC Pin
0 1 Transmit Clock - /TRxC Pin
1 0 Transmit Clock - BR Generator Output
1 1 Transmit Clock - DPLL Output
0 0 Receive Clock - /RTxC Pin
0 1 Receive Clock - /TRxC Pin
1 0 Receive Clock - BR Generator Output
1 1 Receive Clock - DPLL Output
/RTxC Xtal//No Xtal
Write Register 10
D7 D6 D5 D4 D3 D2 D1 D0
0 0 NRZ
0 1 NRZI
1 0 FM1 (Transition = 1)
1 1 FM0 (Transition = 0)
(j)
(k)
6 Bit//8 Bit Sync
Loop Mode
Abort//Flag On Underrun
Mark//Flag Idle
Go Active On Poll
Write Register 12
D7 D6 D5 D4 D3 D2 D1 D0
CRC Preset I//O
(l)
TC0
TC1
TC2
TC3
Lower Byte of
TC4
Time Constant
TC5
TC6
TC7
Figure 50. Write Register Bit Functions (Continued)
2-40
DS971800500