Z80181 Datasheet, PDF (54/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
AC CHARACTERISTICS (Continued)
Z180 MPU Timing
Z80181
SMART ACCESS CONTROLLER SAC^™
Ø
/DREQi
(At level
sense)
/DREQi
(At edge
sence)
/TENDi
ST
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi)
T1
T2
Tw
T3
T1
44
45 ^[1]
44
45 ^[2]
46
[3]
17
18
[4]
47
DMA Control Signals
[1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3.
[2] tDRQS and tDRQH are specified for the rising edge of clock.
[3] DMA cycle starts.
[4] CPU cycle starts.
Figure 63. DMA Control Signals
2-54
DS971800500