Z80181 Datasheet, PDF (34/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
SCC REGISTERS (Continued)
Read Register 0
D7 D6 D5 D4 D3 D2 D1 D0
Z80181
SMART ACCESS CONTROLLER SAC^™
Read Register 2
D7 D6 D5 D4 D3 D2 D1 D0
Rx Character Available
Zero Count
Tx Buffer Empty
DCD
Sync/Hunt
CTS
Tx Underrun/EOM
Break/Abort
V0
V1
V2
V3
Interrupt
V4
Vector *
V5
V6
V7
(a)
* Modified if VIS bit in Write register 9 is set.
(c)
Read Register 1
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 3
D7 D6 D5 D4 D3 D2 D1 D0
All Sent
Residue Code 2
Residue Code 1
Residue Code 0
Parity Error
Rx Overrun Error
CRC/Framing Error
End of Frame (SDLC)
(b)
(d)
Figure 49. SCC Read Register Bit Functions
0
0
0
Ext/Status IP
Tx IP
Rx IP
0
0
2-34
DS971800500