Z80181 Datasheet, PDF (28/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
DMA REGISTERS (Continued)
Z80181
SMART ACCESS CONTROLLER SAC^™
DCNTL
Bit MWI1 MWI0
Upon Reset
1
1
R/W R/W R/W
IWI1
1
R/W
Addr 32h
IWI0 DMS1 DMS0 DIM1 DIM0
1
0
0
0
0
R/W R/W R/W R/W R/W
DMA Ch 1 I/O Memory
Mode Select
/DREQi Select, i = 1, 0
I/0 Wait Insertion
Memory Wait Insertion
MWI1, 0 No. of Wait States
00
0
01
1
10
2
11
3
IWI1, 0
00
01
10
11
No. of Wait States
0
2
3
4
DMSi
1
0
Sense
Edge Sense
Level Sense
DM1, 0
00
01
10
11
Transfer Mode
M - I/O
M - I/O
I/O - M
I/O - M
Address Increment/Decrement
MAR1+1
MAR1-1
IAR1 Fixed
IAR1 Fixed
IAR1 Fixed
IAR1 Fixed
MAR1+1
MAR1-1
Figure 37. DMA/WAIT Control Register
2-28
DS971800500