Z80181 Datasheet, PDF (60/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
AC CHARACTERISTICS (Continued)
Z180^™ MPU Timing
Z80181
SMART ACCESS CONTROLLER SAC^™
Table A. Z180 CPU &180 Peripherals Timing (Continued)
No
Symbol
Parameter
Z8018110
Min
Max
Unit
47
tTED2
Clock Fall to /TENDi Rise Delay
48
tED1
Clock Rise to E Rise Delay
49
tED2
Clock Edge to E Fall Delay
50
PWEH
E Pulse Width (High)
51
PWEL
E Pulse Width (Low)
50
ns
60
ns
60
ns
55
ns
110
ns
52
tEr
Enable Rise Time
53
tEf
Enable Fall Time
54
tTOD
Clock Fall to Timer Output Delay
55
tSTDI
CSI/O Tx Data Delay Time
(Internal Clock Operation)
56
tSTDE
CSI/O Tx Data Delay Time
(External Clock Operation)
20
ns
20
ns
150
ns
150
ns
7.5tcyc+150 ns
57
tSRSI
CSI/O Rx Data Setup Time
1
tcyc
(Internal Clock Operation)
58
tSRHI
CSI/O Rx Data Hold Time
1
tcyc
(Internal Clock Operation)
59
tSRSE
CSI/O Rx Data Setup Time
1
tcyc
(External Clock Operation)
60
tSRHE
CSI/O Rx Data Hold Time
1
tcyc
(External Clock Operation)
61
tRES
62
tREH
63
tOSC
64
tEXr
65
tEXf
/RESET Setup Time to Clock Fall
/RESET Hold Time from Clock Fall
Oscillator Stabilization Time
External Clock Rise Time (EXTAL)
External Clock Fall Time (EXTAL)
80
ns
50
ns
20
ms
25
ns
25
ns
66
tRr
/RESET Rise Time
67
tRf
/RESET Fall Time
68
tIr
Input Rise Time
(Except EXTAL, /RESET)
69
tIf
Input Fall Time
(Except EXTAL, /RESET)
70
TdCS(A) Address Valid to /ROMCS, /RAMCS
Valid Delay
50
ns
50
ns
100
ns
100
ns
20
ns
2-60
DS971800500