Z80181 Datasheet, PDF (42/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
PIA Control Registers
Z80181
SMART ACCESS CONTROLLER SAC^™
PIA1 Data Direction Register (P1DDR, I/O Address E0h),
PIA1 Data Port (P1DP, I/O address E1h), PIA2 Data Direc-
tion Register (P2DDR, I/O Address E2h) and PIA2 Data
Register (P2DP, I/O Address E3h). These four registers are
shown in Figures 51-54. Note that if the CTC/PIA bit in the
System Configuration Register is set to one, the CTC I/O
functions override the PIA1 function, and programming of
P1DDR is ignored.
E0H
76543210
E2H
76543210
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
1 - Input
0 - Output
Figure 51. PIA 1 Data Direction Register
Figure 53. PIA 2 Data Direction Register
E1H
76543210
PIA 1
I/O Data
Figure 52. PIA 1 Data Register
E3H
76543210
PIA 2
I/O Data
Figure 54. PIA 2 Data Register
The Data Port is the register to/from the 8-bit parallel port.
At power on Reset, they are initialized to 1.
The Data Direction Register has eight control bits. Individ-
ual bits specify each bit's direction. When the bit is set to
a "1", the bit becomes an input, otherwise it is an output. On
reset, these registers are initialized to 1, resulting in all lines
being inputs.
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DS971800500