Z80181 Datasheet, PDF (52/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
AC CHARACTERISTICS (Continued)
Z180 MPU Timing
Ø
31
30
/INTI
32
/NMI
C7
/INTSCC [4]
Z80181
SMART ACCESS CONTROLLER SAC^™
/M1 [1]
29
/IORQ [1]
/Data IN [1]
38
/MREQ [2]
40
39
/RFSH [2]
34
33
34
33
/BUSREQ
35
36
/BUSACK
Address
Data /MREQ,
/RD, /WR,
/IORQ
37
42
[3]
/HALT
Notes:
[1] During /INT0 acknowledge cycle [3] Output buffer is off at this point
[2] During refresh cycle
[4] Refer to Table C, parameter 7
16
15
42
37
43
Figure 61. CPU Timing
(/INT0 Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode
HALT Mode, SLEEP Mode, SYSTEM STOP Mode)
2-52
DS971800500