Z80181 Datasheet, PDF (22/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
ASCI CHANNELS CONTROL REGISTERS (Continued)
Z80181
SMART ACCESS CONTROLLER SAC^™
TDR0
Write Only
Addr 06h
76543210
TSR0
Read Only
Addr 08h
xxxxxxxx
Transmit Data
Received Data
Figure 13. ASCI Transmit Data Register (Ch. 0)
Figure 15. ASCI Receive Data Register (Ch. 0)
TDR1
Write Only
Addr 07h
76543210
Transmit Data
Figure 14. ASCI Transmit Data Register (Ch. 1)
TSR1
Read Only
Addr 09h
xxxxxxxx
Received Data
Figure 16. ASCI Receive Data Register (Ch. 1)
CSI/O Registers
CNTR
Addr 0Ah
Bit EF EIE RE TE
- SS2 SS1 SS0
Upon Reset
0
0
0
0
1
1
1
1
R/W R R/W R/W R/W
R/W R/W R/W
Speed Select
Transmit Enable
Receive Enable
End Interrupt Enable
End Flag
SS2, 1, 0
000
001
010
011
Baud Rate
Ø ÷ 20
Ø ÷ 40
Ø ÷ 80
Ø ÷ 100
SS2, 1, 0
Baud Rate
100 Ø ÷ 320
101 Ø ÷ 640
110 Ø ÷ 1280
111 External Clock
(Frequency < Ø ÷ 20)
Figure 17. CSI/O Control Register
2-22
DS971800500