Z80181 Datasheet, PDF (61/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
AC CHARACTERISTICS (Continued)
CTC Timing
Figure 69 shows the timing for the on-chip CTC. Param-
eters referenced in this figure appear in Table B.
Z80181
SMART ACCESS CONTROLLER SAC^™
Clock
CLK/TRG
Counter
CLK/TRG
Timer
ZC/TO
/INT
5
6
7
2
9
8
3
10
11
1
4
Figure 69. CTC Timing
No Symbol
Table B. CTC Timing Parameters
Parameter
Z8018110
Min
Max
1
TdCr(INTf)
Clock Rise to /INT Fall Delay
(TcC+100)
2
TsCTRr(Cr)c CLK/TRG Rise to Clock Rise
Setup Time for Immediate Count
90
3
TsCTR(Ct)
CLK/TRG Rise to Clock Rise
Setup Time for Enabling of Prescaler
90
On Following Clock Rise
4
TdCTRr(INTf) CLK/TRG Rise to /INT Fall Delay
TsCTR(C) Satisfied
(1)+(3)
TsCTR(C) Not Satisfied
TcC+(1)+(3)
5
TcCTR
6
TwCTRh
7
TwCTRl
8
TrCTR
CLK/TRG Cycle Time
CLK/TRG Width (Low)
CLK/TRG Width (High)
CLK/TRG Rise Time
(2TcC)
DC
90
DC
90
DC
30
9
TfCTR
CLK/TRG Fall Time
30
10 TdCr(ZCr)
Clock Rise to ZC/TO Rise Delay
80
11 TdCf(ZCf)
Clock Fall to ZC/TO Fall Delay
80
Notes for Table B:
[B1] Timer Mode
[B2] Counter Mode
[B3] Counter Mode Only. When using a cycle time less than 3TcC, parameter #2 must be met.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
[B1]
[B2]
[B1]
[B2]
[B2]
[B3]
DS971800500
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