Z80181 Datasheet, PDF (51/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Z80181
SMART ACCESS CONTROLLER SAC^™
T1
T2
Twa
T3
T1
Ø
6
Address
70
70
/ROMCS
/RAMCS
19
20
/WAIT
7
28
11
/IORQ
27
9
12
11
/RD
22
/WR
25, 25a
24
15
16
Data IN
23
21
26
Data OUT
[1]
"H"
ST
[1] Output buffer is off at this point.
[2] Memory Read/Write cycle timing is the same as this figure, except there is
no automatic wait status (Twa), and /MREQ is active instead of /IORQ.
Figure 60b. I/O Read/Write, Memory Read/Write Timing
DS971800500
2-51