Z80181 Datasheet, PDF (20/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
ASCI CHANNELS CONTROL REGISTERS (Continued)
Z80181
SMART ACCESS CONTROLLER SAC^™
CNTLB1
Addr 03h
Bit
MPBT MP
/CTS/
PS
PE0
DR
SS2 SS1
SS0
Upon Reset Invalid 0
0
0
0
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Clock Source and Speed Select
Divide Ratio
Parity Even or Odd
Read - Status of /CTS pin
Write - Select PS
Multiprocessor
Multiprocessor Bit Transmit
General
Divide Ratio
SS, 2, 1, 0
000
001
010
011
100
101
110
111
PS = 0
(Divide Ratio = 10)
DR = 0 (x16)
Ø ÷ 160
Ø ÷ 320
Ø ÷ 640
Ø ÷ 1280
Ø ÷ 2560
Ø ÷ 5120
Ø ÷ 10240
DR = 1 (x64)
Ø ÷ 640
Ø ÷ 1280
Ø ÷ 2580
Ø ÷ 5120
Ø ÷ 10240
Ø ÷ 20480
Ø ÷ 40960
External Clock (Frequency < Ø ÷ 40)
PS = 1
(Divide Ratio = 30)
DR = 0 (x16)
Ø ÷ 480
Ø ÷ 960
Ø ÷ 1920
Ø ÷ 3840
Ø ÷ 7680
Ø ÷ 15360
Ø ÷ 30720
DR = 1 (x64)
Ø ÷ 1920
Ø ÷ 3840
Ø ÷ 7680
Ø ÷ 15360
Ø ÷ 30720
Ø ÷ 61440
Ø ÷ 122880
Figure 10. ASCI Control Register B (Ch. 1)
2-20
DS971800500