Z80181 Datasheet, PDF (35/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Read Register 6 *
D7 D6 D5 D4 D3 D2 D1 D0
BC0
BC1
BC2
BC3
BC4
BC5
BC6
BC7
* Can only be accessed if the SDLC FIFO enhancement
is enabled (WR15 bit D2 set to 1)
(e) SDLC FIFO Status and Byte Count (LSB)
Z80181
SMART ACCESS CONTROLLER SAC^™
Read Register 10
D7 D6 D5 D4 D3 D2 D1 D0
0
On Loop
0
0
Loop Sending
0
Two Clocks Missing
One Clock Missing
(g)
Read Register 7 *
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 12
D7 D6 D5 D4 D3 D2 D1 D0
BC8
BC9
BC10
BC11
BC12
BC13
FDA: FIFO Available Status
1 Status Reads from FIFO
FOS: FIFO Overflow Status
1 FIFO Overflowed
0 Normal
* Can only be accessed if the SDLC FIFO enhancement
is enabled (WR15 bit D2 set to 1)
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
(h)
(f) SDLC FIFO Status and Byte Count (MSB)
Figure 49. SCC Read Register Bit Functions (Continued)
Lower Byte
of Time Constant
DS971800500
2-35