Z80181 Datasheet, PDF (53/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
T1
Ø
Address
/IORQ
/RD
/WR
I/O Read Cycle
T2
Tw
T3
Z80181
SMART ACCESS CONTROLLER SAC^™
I/O Write Cycle
T1
T2
Tw
T3
27
28
27
28
9
13
22
24
Figure 62. CPU Timing (/IOC = 0)
(I/O Read Cycle, I/O Write Cycle)
DS971800500
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