Z80181 Datasheet, PDF (55/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Ø
E
(Memory
Read/Write)
E
(I/O Read)
E
(I/O Read)
D7-D0
Z80181
SMART ACCESS CONTROLLER SAC^™
T1
T2
Tw
Tw
T3
48
49
48
49
48
49
15
16
(a) E Clock Timing
(Memory Read/Write Cycle, I/O Read/Write Cycle)
Ø
48
48
BUS RELEASE Mode
E SLEEP Mode
SYSTEM STOP Mode
(b) E Clock Timing
(BUS RELEASE Mode, SLEEP Mode, SYSTEM STOP Mode)
Figure 64. E Clock Timing
DS971800500
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