Z80181 Datasheet, PDF (17/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
PROGRAMMING (Continued)
Table 1. I/O Control Register Address
Address Register
00h
to 3Fh
E0h
E1h
Z181 MPU Control Registers
(Relocatable to 040h-07Fh, or 080h-0BFh)
PIA1 Data Direction Register (P1DDR)
PIA1 Data Port (P1DP)
E2h
PIA2 Data Direction Register (P2DDR)
E3h
PIA2 Data Register (P2DP)
E4h
CTC Channel 0 Control Register (CTC0)
E5h
CTC Channel 1 Control Register (CTC1)
E6h
CTC Channel 2 Control Register (CTC2)
E7h
CTC Channel 3 Control Register (CTC3)
E8h
SCC Control Register (SCCCR)
E9h
SCC Data Register (SCCDR)
EAh
RAM Upper Boundary Address Register
(RAMUBR)
EBh
RAM Lower Boundary Address Register
(RAMLBR)
ECh
ROM Address Boundary Register (ROMBR)
EDh
System Configuration Register (SCR)
EEh
Reserved
EFh
Reserved
Z80181
SMART ACCESS CONTROLLER SAC^™
Z181 MPU Control Registers
The I/O address for these registers can be relocated in 64
byte boundaries by programming of the I/O Control Reg-
ister (Address xx111111b).
Do not relocate these registers to address from 0C0h since
this will cause an overlap of the Z180 registers and the 16
registers of the Z181 (address 0E0h to 0EFh).
Also, the OMCR register (Address: xx111101b) must be
programmed as 0x0xxxxxb (x: don’t care) as a part of the
initialization procedure. The M1E bit (Bit D7) of this register
must be programmed as 0 or the interrupt daisy chain is
corrupted. The /IOC bit (Bit D5) of this register is pro-
grammed as 0 so that the timing of the /RD and /IORQ
signals are compatible with Z80 peripherals.
For detailed information, refer to the Z180 Technical Manual.
DS971800500
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