Z80181 Datasheet, PDF (30/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
System Control Registers
Z80181
SMART ACCESS CONTROLLER SAC^™
IL
Addr 33h
Bit IL7 IL6 IL5
-
-
-
-
-
Upon Reset
0
0
0
0
0
0
0
0
R/W R/W R/W R/W
Interrupt Vector Low
Figure 41. Interrupt Vector Low Register
ITC
Addr 34h
Bit TRAP UFO -
-
- ITE2 ITE1 ITE0
Upon Reset
0
0
1
1
1
0
0
1
R/W R/W R
R/W R/W R/W
Figure 42. INT/TRAP Control Register
/INT Enable 2, 1, 0
Undefined Fetch Object
TRAP
RCR
Addr 36h
Bit REFE REFW -
-
-
- CYC1 CYC0
Upon Reset
1
1
1
1
1
1
0
0
R/W R/W R/W
R/W R/W
Cycle Select
Refresh Wait State
Refresh Enable
CYC1, 0
00
01
10
11
Interval of Refresh Cycle
10 states
20 states
40 states
80 states
Figure 43. Refresh Control Register
2-30
DS971800500