Z80181 Datasheet, PDF (46/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Data Bus Direction
Table 4 shows the state of the SAC’s data bus when in SAC
bus master condition.
Z80181
SMART ACCESS CONTROLLER SAC^™
Table 4. Data Bus Direction (Z181 Is Bus Master)
I/O And Memory Transactions
I/O
I/O
I/O
I/O
Write
Write To Read From Write To Read From To
On-Chip On-Chip Off-Chip Off-Chip Memory
Peripherals Peripherals Peripheral Peripheral
(SCC/CTC/ (SCC/CTC/
PIA1/PIA2) PIA1/PIA2)
Read Refresh
From
Memory
Z80181
Idle
Mode
Z80181 Data Bus Out
Z
(REME Bit = 0)
Out
In
Out
In
Z
Z
Z80181 Data Bus Out
Out
(REME Bit = 1)
Out
In
Out
In
Z
Z
Interrupt Acknowledge Transaction
Intack For Intack For
On-Chip Off-Chip
Peripheral Peripheral
(SCC/CTC)
Z80181 Data Bus Z
In
(REME Bit = 0)
Z80181 Data Bus Out
In
(REME Bit = 1)
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DS971800500