Z80181 Datasheet, PDF (27/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Z80181
SMART ACCESS CONTROLLER SAC^™
DSTAT
Bit DE1
Upon Reset
0
R/W R/W
DE0 /DWE1 /DWE0 DIE1
0
1
1
0
R/W W
W R/W
DIE0
0
R/W
Addr 30h
- DIME
1
0
R
DMA Master Enable
DMA Interrupt Enable 1, 0
DMA Enable Bit Write Enable 1, 0
DMA Enable Ch 1, 0
Figure 35. DMA Status Register
DMODE
Bit
-
-
Upon Reset
1
1
R/W
DM1
0
R/W
DM0
0
R/W
SM1
0
R/W
Addr 31h
SM0 MMOD -
0
0
1
R/W R/W
Memory MODE Select
Ch 0 Source Mode 1, 0
Ch 0 Destination Mode 1, 0
DM1, 0 Destination Address
00
M
DAR0+1
01
M
DAR0-1
10
M
DAR0 Fixed
11
I/O
DAR0 Fixed
SM1, 0
00
01
10
11
Source
M
M
M
I/O
Address
SAR0+1
SAR0-1
SAR0 Fixed
SAR0 Fixed
MMOD
Mode
0
Cycle Steal Mode
1
Burst Mode
Figure 36. DMA Mode Registers
DS971800500
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