Z80181 Datasheet, PDF (36/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
SCC REGISTERS (Continued)
Read Register 13
D7 D6 D5 D4 D3 D2 D1 D0
Z80181
SMART ACCESS CONTROLLER SAC^™
Read Register 15
D7 D6 D5 D4 D3 D2 D1 D0
TC8
TC9
TC10
TC11
TC12
TC13
TC14
TC15
Upper Byte
of Time Constant
(i)
(j)
Figure 49. SCC Read Register Bit Functions (Continued)
0
Zero Count IE
0
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
Write Registers
The SCC contains fifteen write registers that are pro-
grammed to configure the operating modes of the chan-
nel. With the exception of WR0, programming the write
registers is a two step operation. The first operation is a
pointer written to WR0 that points to the selected register.
The second operation is the actual control word that is
written into the register to configure the SCC channel
(Figure 50).
Table 3. SCC Write Registers
Bit
WR0
WR1
WR2
WR3
WR4
WR5
WR6
WR7
Description
Register Pointers, various initialization
commands
Transmit and Receive interrupt enables,
WAIT/DMA commands
Interrupt Vector
Receive parameters and control modes
Transmit and Receive modes and parameters
Transmit parameters and control modes
Sync Character or SDLC address
Sync Character or SDLC flag
Bit Description
WR8
WR9
WR10
WR11
WR12
WR13
WR14
WR15
Transmit buffer
Master Interrupt control and reset commands
Miscellaneous transmit and receive control bits
Clock mode controls for receive and transmit
Lower byte of baud rate generator
Upper byte of baud rate generator
Miscellaneous control bits
External status interrupt enable control
2-36
DS971800500