Z80181 Datasheet, PDF (47/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Table 5 shows the state of the SAC’s data bus when the
Z80181 is NOT in bus master condition.
Z80181
SMART ACCESS CONTROLLER SAC^™
Table 5. Data Bus Direction for External Bus Master (Z80181 Is Not Bus Master)
I/O And Memory Transactions
I/O
I/O
I/O
I/O
Write
Write To Read From Write To Read From To
On-Chip On-Chip Off-Chip Off-Chip Memory
Peripherals Peripherals Peripheral Peripheral
(SCC/CTC/ (SCC/CTC/
PIA1/PIA2) PIA1/PIA2)
Read Refresh
From
Memory
Z80181
Idle
Mode
Z80181 Data Bus In
(REME Bit = 0)
Out
Z
Z
Z
In
Z
Z
Z80181 Data Bus In
(REME Bit = 1)
Out
Z
Z
Z
In
Z
Z
Interrupt Acknowledge Transaction
Intack For
On-Chip
Peripheral
(SCC/CTC)
Intack For
Off-Chip
Peripheral
Z80181 Data Bus Out
In
(REME Bit = 0)
Z80181 Data Bus Out
In
(REME Bit = 1)
The word “OUT” means that the Z181 data bus direction is
in output mode, “IN” means input mode, and “HI-Z” means
high impedance.
“REME” stands for “ROM Emulator Mode” and is the status
of D2 bit in the System Configuration Register.
DS971800500
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