Z80181 Datasheet, PDF (15/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Each of the Counter/Timer Channels, designated Chan-
nels 0-3, have an 8-bit prescaler (when used in timer
mode) and its own 8-bit counter to provide a wide range of
count resolution. Each of the channels have their own
Clock/Trigger input to quantify the counting process and
an output to indicate zero crossing/timeout conditions.
Z80181
SMART ACCESS CONTROLLER SAC^™
These signals are multiplexed with the Parallel Interface
Adapter 1 (PIA1). With only one interrupt vector pro-
grammed into the logic unit, each channel can generate a
unique interrupt vector in response to the interrupt ac-
knowledge cycle.
Internal
Control
Logic
Data
Control
CPU
BUS
I/O
Interrupt
/INT
Logic
IEI
IEO
Counter/
Timer
Logic
4
ZC/TO
4
Mutiplexed
with PIA1
CLK/TRG
/RESET
Figure 5. CTC Block Diagram
Parallel Interface Adapter (PIA)
The SAC has two 8-bit Parallel Interface Adapter (PIA)
Ports. The ports are referred to as PIA1 and PIA2. Each port
has two associated control registers; a Data Register and
a register to determine each bit’s direction (input or out-
put). PIA1 is multiplexed with the CTC I/O pins. When the
CTC I/O feature is selected, the CTC I/O functions override
the PIA1 feature. Mode Selection is made through the
System Configuration Register (Address: EDh; Bit D0).
PIA1 has Schmitt-triggered inputs to have a better noise
margin. These ports are inputs after reset.
Clock Generator
The SAC uses the Z181 MPU’s on-chip clock generator to
supply system clock. The required clock is easily gener-
ated by connecting a crystal to the external terminals
(XTAL, EXTAL). The clock output runs at half the crystal
frequency. The system clock inputs of the SCC and the
CTC are internally connected to the PHI output of the Z181
MPU.
C1
XTAL
Crystal
Inputs
C2
EXTAL
Figure 6. Circuit Configuration For Crystal
DS971800500
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