Z80181 Datasheet, PDF (43/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Z80181
SMART ACCESS CONTROLLER SAC^™
REGISTERS FOR SYSTEM CONFIGURATION
There are four registers to determine system configuration
with the Z181. These registers are: RAM upper boundary
address register (RAMUBR, I/O address EAh), RAM lower
boundary address register (RAMLBR, I/O address EBh),
ROM address boundary register (ROMBR, I/O address
ECh) and System Configuration Register (SCR, I/O ad-
dress EDh).
RAMLBR, /RAMCS is asserted. (Figure 13) The A18 signal
from the CPU is taken before it is multiplexed with “T_OUT”.
In the case that these register are programmed to overlap,
/ROMCS takes priority over /RAMCS (/ROMCS is asserted
and /RAMCS is inactive).
Chip Select signals are going active for the address range:
ROM Address Boundary Register
(ROMBR, I/O Address ECh)
This register specifies the address range for the /ROMCS
signal. When accessed memory addresses are less than
or equal to the value programmed in this register, the
/ROMCS signal is asserted (Figure 55).
The A18 signal from the CPU is obtained before it is
multiplexed with “TOUT”. This signal can be forced to “1”
(inactive state) by setting Bit D5 of the System Configura-
tion Register, to allow the user to overlay the RAM area over
the ROM area. At power-up reset, this register contains all
1's so that /ROMCS is asserted for all addresses.
RAM Lower Boundary Address Register (RAMLBR,
I/O Address EBh) and RAM Upper Boundary
Address Register (RAMUBR, I/O Address EAh)
These two registers specify the address range for the
/RAMCS signal. When accessed memory addresses are
less than or equal to the value programmed in the RAMUBR
and greater than or equal to the value programmed in the
/ROMCS: (ROMBR) ≥ A19-A12 ≥ 0
/RAMCS: (RAMUBR) ≥ A19-A12 > (RAMLBR)
These registers are set to “FFh” at power-on Reset, and the
boundary addresses of ROM and RAM are the following:
ROM lower boundary address
(fixed) = 00000h
ROM upper boundary address
(ROMBR register) = 0FFFFFh
RAM lower boundary address
(RAMLBR register) = 0FFFFFh
RAM upper boundary address
(RAMUBR register) = 0FFFFFh
Since /ROMCS takes priority over /RAMCS, the latter will
never be asserted until the value in the ROMBR and
RAMLBR registers are re-initialized to lower values.
EAH
76543210
EBH
76543210
A12
A12
A13
A13
A14
A14
A15
A15
A16
A16
A17
A17
A18
A18
A19
A19
Figure 55. RAM Upper Boundary Register
Figure 56. RAM Lower Boundary Register
DS971800500
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