Z80181 Datasheet, PDF (18/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
ASCI CHANNELS CONTROL REGISTERS
Z80181
SMART ACCESS CONTROLLER SAC^™
CNTLA0
Bit MPE RE
Upon RESET
R/W
0
0
R/W R/W
Addr 00h
TE
/RTS0
MPBR/
EFR
MOD2
MOD1
MOD0
0
1
x
0
0
0
R/W R/W R/W R/W R/W R/W
MODE Selection
0
0
0 Start + 7-Bit Data + 1 Stop
0
0
1 Start + 7-Bit Data + 2 Stop
0
1
0 Start + 7-Bit Data + Parity + 1 Stop
0
1
1 Start + 7-Bit Data + Parity + 2 Stop
1
0
0 Start + 8-Bit Data + 1 Stop
1
0
1 Start + 8-Bit Data + 2 Stop
1
1
0 Start + 8-Bit Data + Parity + 1 Stop
1
1
1 Start + 8-Bit Data + Parity + 2 Stop
Read - Multiprocessor Bit Receive
Write - Error Flag Reset
Request To Send
Transmit Enable
Receive Enable
Multiprocessor Enable
Figure 7. ASCI Control Register A (Ch. 0)
CNTLA1
Bit MPE RE
Upon RESET
R/W
0
0
R/W R/W
Addr 01h
TE
CKA1D
MPBR/
EFR
MOD2
MOD1
MOD0
0
1
x
0
0
0
R/W R/W R/W R/W R/W R/W
MODE Selection
0
0
0 Start + 7-Bit Data + 1 Stop
0
0
1 Start + 7-Bit Data + 2 Stop
0
1
0 Start + 7-Bit Data + Parity + 1 Stop
0
1
1 Start + 7-Bit Data + Parity + 2 Stop
1
0
0 Start + 8-Bit Data + 1 Stop
1
0
1 Start + 8-Bit Data + 2 Stop
1
1
0 Start + 8-Bit Data + Parity + 1 Stop
1
1
1 Start + 8-Bit Data + Parity + 2 Stop
Read - Multiprocessor Bit Receive
Write - Error Flag Reset
CKA1 Disable
Transmit Enable
Receive Enable
Multiprocessor Enable
Figure 8. ASCI Control Register A (Ch. 1)
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DS971800500