Z80181 Datasheet, PDF (59/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

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Z80181
SMART ACCESS CONTROLLER SAC^™
Table A. Z180 CPU & 180 Peripherals Timing (Continued)
Symbol
Parameter
Z8018110
Min
Max
Unit
tAH
tMED2
tRDD2
tM1D2
tDRS
Address Hold Time
(/MREQ, /IORQ, /RD, /WR)
Clock Fall to /MREQ Rise Delay
Clock Fall to /RD Rise Delay
Clock Rise to /M1 Rise Delay
Data Read Setup Time
10
ns
50
ns
50
ns
60
ns
25
ns
tDRH
tSTD1
tSTD2
tWS
tWH
Data Read Hold Time
Clock Fall to ST Fall
Clock Fall to ST Rise
/WAIT Setup Time to Clock Fall
/WAIT Hold time from Clock Fall
0
ns
60
ns
60
ns
30
ns
30
ns
tWDZ
tWRD1
tWDO
tWRD2
tWRP
Clock Rise to Data Float Delay
Clock Rise to /WR Fall Delay
/WR fall to Data Out Delay
Clock Fall to /WR Rise
/WR Pulse Width
(Memory Write Cycles)
60
ns
50
ns
10
ns
50
ns
110
ns
tWDH
tIOD1
tIOD2
/WR Pulse Width (I/O Write Cycles)
Write Data Hold Time from /WR Rise
Clock Fall to /IORQ Fall Delay
(/IOC=1)
Clock Rise to /IORQ Fall Delay
(/IOC=0)
Clock Fall /IOQR Rise Delay
210
ns
10
ns
50
ns
55
ns
50
ns
tIOD3
/M1 Fall to /IORQ Fall Delay
200
ns
tINTS
/INT Setup Time to Clock Fall
30
ns
tINTH
/INT Hold Time from Clock Fall
30
ns
tNMIW
/NMI Pulse Width
80
ns
tBRS
/BUSREQ Setup Time to Clock Fall
30
ns
tBRH
/BUSREQ Hold Time from Clock Fall
30
ns
tBAD1
Clock Rise to /BUSACK Fall Delay
60
ns
tBAD2
Clock Fall to /BUSACK Rise Delay
60
ns
tBZD
Clock Rise to Bus Floating Delay Time
80
ns
tMEWH
tMEWL
tRFD1
tRFD2
tHAD1
/MREQ Pulse Width (High)
/MREQ Pulse Width (Low)
Clock Rise to /RFSH Fall Delay
Clock Rise to /RFSH Rise Delay
Clock Rise to /HALT Fall Delay
70
ns
80
ns
60
ns
60
ns
50
ns
tHAD2
tDRQS
tDRQH
tTED1
Clock Rise to /HALT Rise Delay
/DREQi Setup Time to Clock Rise
/DREQi Hold Time from Clock Rise
Clock Fall to /TENDi Fall Delay
50
ns
30
ns
30
ns
50
ns
DS971800500
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