Z80181 Datasheet, PDF (33/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Time Constant Word
Before a channel can start counting, it must receive a time
constant word. The time constant value may be anywhere
between 1 and 256, with “0” being accepted as a count of
256 (Figure 47).
D7 D6 D5 D4 D3 D2 D1 D0
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
Figure 47. CTC Time Constant Word
Z80181
SMART ACCESS CONTROLLER SAC^™
Interrupt Vector Word
If one or more of the CTC channels have interrupt enabled,
then the Interrupt Vector Word is programmed. Only the
five most significant bits of this word are programmed, and
bit D0 must be “0”. Bits D2-D1 are automatically modified
by the CTC channels after responding with an interrupt
vector (Figure 48).
Addr: E4h
D7 D6 D5 D4 D3 D2 D1 D0
0 Interrupt Vector Word
1 Control Word
Channel Identifier
(Automatically Inserted
by CTC)
0 0 Channel 0
0 1 Channel 1
1 0 Channel 2
1 1 Channel 3
Supplied By User
Figure 48. CTC Interrupt Vector Word
SCC REGISTERS
For more detailed information, please refer to the Z8030/
Z8530 SCC Technical Manual.
Note:
The Address for the Control/Status Register is E8h. The
Address for the Data Register is E9h.
Read Registers
The SCC contains eight read registers. To read the con-
tents of a register (rather than RR0), the program must first
initialize a pointer to WR0 in exactly the same manner as a
write operation. The next I/O read cycle will place the
contents of the selected read registers onto the data bus
(Figure 49).
Table 2. SCC Read Registers
Bit Description
Bit Description
RR0 Transmit and Receive buffer status
RR7 SDLC FIFO byte count and status
and external status.
(only when enabled).
RR1 Special Receive Condition status.
RR8 Receive buffer.
RR2 Interrupt vector (modified if VIS Bit in WR9 is set). RR10 Miscellaneous status bits.
RR3 Interrupt pending bits.
RR12 Lower byte of baud rate.
RR6 SDLC FIFO byte counter lower byte
RR13 Upper byte of baud rate generator time constant.
(only when enabled).
RR15 External Status interrupt information.
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