Z80181 Datasheet, PDF (70/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
AC CHARACTERISTICS (Continued)
Read Write External BUS Master Timing
CLK
1
Address A7-A0
/IORQ
10
/RD
11
Data
/WR
12
Data
2
3
4
3
5
7
6
Data OUT
3
8
9
Data IN
Z80181
SMART ACCESS CONTROLLER SAC^™
Figure 76. Read/Write External BUS Master Timing
Table H. External Bus Master Interface Timing (Read/Write Cycles)
No Symbol
Parameter
Z8018110
Min
Max
Unit
1
TsA(Cr)
2
TsIO(Cr)
3
Th
4
TsRD(Cr)
5
TdRD(DO)
Address to CLK Rise Setup Time
/IORQ Fall to CLK Rise Setup Time
Hold Time
/RD Fall to CLK Rise Setup Time
/RD Fall to Data Out Delay
20
ns
20
ns
0
20
ns
120
ns
6
TdRIr(DOz)
/RD, /IORQ Rise to Read Data Float
0
7
TsWR(Cr)
/WR Fall to CLK Rise Setup Time
20
ns
8
TsDi(WRf)
Data in to /WR Fall Setup Time
0
9
ThWIr(Di)
/IORQ, /WR Rise to Data In Hold Time
0
10 TsA(IORQf)
Address to /IORQ Fall Setup Time
50
ns
11 TsA(RDf)
Address to /RD Fall Setup Time
50
ns
12 TsA(WRf)
Address to /WR Fall Setup Time
50
ns
2-70
DS971800500