Z80181 Datasheet, PDF (31/74 Pages) Zilog, Inc. – SMART ACCESS CONTROLLER (SAC™)

Zilog
Z80181
SMART ACCESS CONTROLLER SAC^™
OMCR
Addr 3Eh
Bit M1E /M1TE /IOC -
-
-
-
-
Upon Reset
1
1
1
1
1
1
1
1
R/W R/W W R/W
I/O Compatibility
/M1 Temporary Enable
/M1 Enable
Note: This register has to be programmed as 0x0xxxxxb(x:don't care) as a part of Initialization.
Figure 44. Operation Mode Control Register
ICR
Addr 3Fh
Bit IOA7 IOA6 IOSTP -
-
-
-
-
Upon Reset
0
0
0
1
1
1
1
1
R/W R/W R/W R/W
I/O Stop
I/O Address
Combination of 11
is reserved
Figure 45. I/O Control Register
DS971800500
2-31