DS152 Datasheet, PDF (8/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100Ω differential load only, i.e., a 100Ω resistor between the two receiver pins. The
V_OH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see the
Virtex-6 FPGA SelectIO Resources User Guide.
Table 11: LVPECL DC Specifications
Symbol
DC Parameter
Min
V_OH
V_OL
V_ICM
V_IDIFF
Output High Voltage
Output Low Voltage
Input Common-Mode Voltage
Differential Input Voltage⁽¹⁾⁽²⁾
V_CC – 1.025
V_CC – 1.81
0.6
0.100
Notes:
1. Recommended input maximum voltage not to exceed V_CCAUX + 0.2V.
2. Recommended input minimum voltage not to go below –0.5V.
Typ
1.545
0.795
–
–
Max
V_CC – 0.88
V_CC – 1.62
2.2
1.5
Units
V
V
V
V
eFUSE Read Endurance
Table 12 lists the maximum number of read cycle operations expected. For more information, see the Virtex-6 FPGA
Configuration User Guide.
Table 12: eFUSE Read Endurance
Symbol
DNA_CYCLES
AES_CYCLES
Description
-3
Number of DNA_PORT READ operations or JTAG ISC_DNA read
command operations. Unaffected by SHIFT operations.
Number of JTAG FUSE_KEY or FUSE_CNTL read command
operations. Unaffected by SHIFT operations.
Speed Grade
-2
-1
30,000,000
30,000,000
Units
-1L
Read
Cycles
Read
Cycles
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
8