DS152 Datasheet, PDF (21/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at:
http://www.xilinx.com/technology/protocols/pciexpress.htm
Table 39: Maximum Performance for PCI Express Designs
Symbol
Description
F_PIPECLK
F_USERCLK
F_DRPCLK
Pipe clock maximum frequency
User clock maximum frequency
DRP clock maximum frequency
Speed Grade
Units
-3
-2
-1
-1L
250
250
250
250
MHz
500
500
250
250
MHz
250
250
250
250
MHz
System Monitor Analog-to-Digital Converter Specification
Table 40: Analog-to-Digital Specifications
Parameter
Symbol
Comments/Conditions
Min Typ Max
AV_DD = 2.5V ± 5%, V_REFP = 1.25V, V_REFN = 0V, ADCCLK = 5.2 MHz, T_j = –40°C to 100°C, Typical values at T_j=+35°C
DC Accuracy: All external input channels. Both unipolar and bipolar modes.
Resolution
10
–
–
Integral Nonlinearity
INL
–
–
±1
Differential Nonlinearity
Unipolar Offset Error ⁽¹⁾
Bipolar Offset Error ⁽¹⁾
DNL
No missing codes (T_MIN to T_MAX)
Guaranteed Monotonic
Uncalibrated
Uncalibrated measured in bipolar mode
–
–
±0.9
–
±2
±30
–
±2
±30
Gain Error
Uncalibrated - External Reference
–
±0.2
±2
Bipolar Gain Error ⁽¹⁾
Uncalibrated - Internal Reference
Uncalibrated - External Reference
–
±2
–
–
±0.2
±2
Uncalibrated - Internal Reference
–
±2
–
Total Unadjusted Error
(Uncalibrated)
TUE
Deviation from ideal transfer function.
External 1.25V reference
–
±10
–
Deviation from ideal transfer function.
Internal reference
–
±20
–
Total Unadjusted Error
(Calibrated)
TUE
Deviation from ideal transfer function.
External 1.25V reference
–
±1
±2
Calibrated Gain Temperature
Coefficient
Variation of FS code with temperature
– ±0.01
–
DC Common-Mode Reject
Conversion Rate⁽²⁾
CMRR_DC V_N = V_CM = 0.5V ± 0.5V,
V_P – V_N = 100mV
–
70
–
Conversion Time - Continuous
Conversion Time - Event
T/H Acquisition Time
DRP Clock Frequency
t_CONV
t_CONV
t_ACQ
DCLK
Number of CLK cycles
Number of CLK cycles
Number of CLK cycles
DRP clock frequency
26
–
32
–
–
21
4
–
–
8
–
80
ADC Clock Frequency
ADCCLK Derived from DCLK
1
–
5.2
CLK Duty cycle
40
–
60
Units
Bits
LSBs
LSBs
LSBs
LSBs
%
%
%
%
LSBs
LSBs
LSBs
LSB/°C
dB
MHz
MHz
%
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
21