DS152 Datasheet, PDF (51/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 68: Global Clock Input Setup and Hold With MMCM
Symbol
Description
Device
Speed Grade
-3
-2
-1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
T_PSMMCMGC/
T_PHMMCMGC
No Delay Global Clock Input and IFF⁽²⁾ XC6VLX75T
with MMCM
1.45/
–0.18
1.57/
–0.18
1.72/
–0.18
XC6VLX130T
1.53/
–0.18
1.65/
–0.18
1.81/
–0.18
XC6VLX195T
1.54/
–0.17
1.66/
–0.17
1.82/
–0.17
XC6VLX240T
1.54/
–0.17
1.66/
–0.17
1.82/
–0.17
XC6VLX365T
1.55/
–0.18
1.67/
–0.18
1.83/
–0.18
XC6VLX550T
N/A
1.84/
2.02/
–0.17 –0.17
XC6VLX760
N/A
2.26/
2.49/
–0.13 –0.13
XC6VSX315T
1.56/
–0.18
1.68/
–0.18
1.84/
–0.18
XC6VSX475T
N/A
1.85/
2.03/
–0.23 –0.23
XC6VHX250T
1.52/
–0.17
1.64/
–0.17
1.80/
–0.17
XC6VHX255T
1.52/
–0.12
1.64/
–0.12
1.80/
–0.12
XC6VHX380T
1.68/
–0.16
1.81/
–0.16
1.99/
–0.16
XC6VHX565T
N/A
1.81/
1.99/
–0.16 –0.16
Units
-1L
1.78/
ns
–0.08
1.87/
ns
–0.07
1.87/
ns
–0.08
1.87/
ns
–0.08
1.87/
ns
–0.07
2.06/
ns
–0.06
2.06/
ns
–0.03
1.89/
ns
–0.08
2.07/
ns
–0.13
N/A
ns
N/A
ns
N/A
ns
N/A
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
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