DS152 Datasheet, PDF (12/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 21: GTX Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
F_GCLK
T_RCLK
T_FCLK
T_DCREF
T_LOCK
T_PHASE
Reference clock frequency range
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
Clock recovery frequency acquisition
time
Clock recovery phase acquisition time
20% – 80%
80% – 20%
Transceiver PLL only
Initial PLL lock
Lock to data after PLL has locked
to the reference clock
X-Ref Target - Figure 3
80%
T_RCLK
All Speed Grades
Min
Typ
Max
62.5
–
650
–
200
–
–
200
–
45
50
55
–
–
1
–
–
200
Units
MHz
ps
ps
%
ms
µs
20%
T_FCLK
ds152_05_042109
Figure 3: Reference Clock Timing Parameters
Table 22: GTX Transceiver User Clock Switching Characteristics⁽¹⁾
Symbol
Description
Conditions
F_TXOUT
F_RXREC
T_RX
T_RX2
T_TX
T_TX2
TXOUTCLK maximum frequency
RXRECCLK maximum frequency
RXUSRCLK maximum frequency
RXUSRCLK2 maximum frequency
TXUSRCLK maximum frequency
TXUSRCLK2 maximum frequency
Internal 20-bit data path
Internal 16-bit data path
Internal 20-bit data path
Internal 16-bit data path
1 byte interface
2 byte interface
4 byte interface
1 byte interface
2 byte interface
4 byte interface
-3
330
412.5
330
412.5
412.5⁽²⁾
376
406.25
206.25
412.5⁽³⁾
376
406.25
206.25
Speed Grade
-2
-1
330
250
412.5
312.5
330
250
412.5
312.5
412.5⁽²⁾
312.5
376
312.5
406.25
312.5
206.25
412.5⁽³⁾
156.25
312.5
376
312.5
406.25
312.5
206.25 156.25
Notes:
1. Clocking must be implemented as described in the Virtex-6 FPGA GTX Transceivers User Guide.
2. 406.25 MHz when the RX elastic buffer is bypassed.
3. 406.25 MHz when the TX buffer is bypassed.
Units
-1L
250
MHz
250
MHz
250
MHz
250
MHz
250
MHz
250
MHz
250
MHz
125
MHz
250
MHz
250
MHz
250
MHz
125
MHz
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
12