DS152 Datasheet, PDF (43/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 57: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
Clock to Outs from Input Register Clock to Output Pins
T_{DSPCKO_{P, CARRYOUT}_{AREG, BREG}_MULT}
CLK (AREG, BREG) to {P, CARRYOUT}
output using multiplier
T_{DSPCKO_{P, CARRYOUT}_{AREG, BREG}}
CLK (AREG, BREG) to {P, CARRYOUT}
output not using multiplier
T_{DSPCKO_{P, CARRYOUT}_CREG}
CLK (CREG) to {P, CARRYOUT} output
T_{DSPCKO_{P, CARRYOUT}_DREG_MULT}
CLK (DREG) to {P, CARRYOUT} output
Clock to Outs from Input Register Clock to Cascading Output Pins
T_{DSPCKO_{ACOUT; BCOUT}_{AREG; BREG}}
CLK (AREG, BREG) to {P, CARRYOUT}
output
T_{DSPCKO_{PCOUT, CARRYCASCOUT,}
MULTSIGNOUT}_{AREG, BREG}_MULT
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
T_{DSPCKO_{PCOUT, CARRYCASCOUT,}
MULTSIGNOUT}_{AREG, BREG}
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
T_{DSPCKO_{PCOUT, CARRYCASCOUT,}
MULTSIGNOUT}_DREG_MULT
CLK (DREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
T_{DSPCKO_{PCOUT, CARRYCASCOUT,}
MULTSIGNOUT}_CREG
CLK (CREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
Maximum Frequency
F_MAX
F_{MAX_PATDET}
F_{MAX_MULT_NOMREG}
F_{MAX_MULT_NOMREG_PATDET}
With all registers used
With pattern detector
Two register multiply without MREG
Two register multiply without MREG
with pattern detect
F_{MAX_PREADD_MULT_NOADREG}
F_{MAX_PREADD_MULT_NOADREG_PATDET}
F_{MAX_NOPIPELINEREG}
Without ADREG
Without ADREG with pattern detect
Without pipeline registers (MREG,
ADREG)
F_{MAX_NOPIPELINEREG_PATDET}
Without pipeline registers (MREG,
ADREG) with pattern detect
-3
3.97
1.70
1.70
3.89
0.66
4.05
1.79
3.98
1.78
600
551
356
327
398
398
266
250
Speed
-2
-1
4.52 5.36
1.93 2.27
1.93 2.27
4.44 5.25
0.76 0.89
4.63 5.49
2.03 2.40
4.54 5.38
2.03 2.40
540 450
483 408
311 262
286 241
347 292
347 292
233 196
219 184
Units
-1L
6.20 ns
2.65 ns
2.80 ns
6.07 ns
1.01 ns
6.39 ns
2.84 ns
6.26 ns
2.99 ns
410 MHz
356 MHz
224 MHz
211 MHz
254 MHz
254 MHz
171 MHz
160 MHz
Configuration Switching Characteristics
Table 58: Configuration Switching Characteristics
Symbol
Description
Power-up Timing Characteristics
T_PL(1)
T_POR(1)
Program Latency
Power-on-Reset
T_ICCK
CCLK (output) delay
T_PROGRAM
Program Pulse Width
Speed Grade
-3
-2
-1
-1L
Units
5
15/55
400
250
5
15/55
400
250
5
15/55
400
250
5
15/55
400
250
ms, Max
ms, Min/Max
ns, Min
ns, Min
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
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