DS152 Datasheet, PDF (37/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 53: CLB Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
Set/Reset
T_SRMIN
T_RQ
T_CEO
F_TOG
SR input minimum pulse width
Delay from SR input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
0.90
0.52
0.41
1412.00
0.90
0.58
0.48
1286.40
0.97
0.68
0.59
1098.00
0.80
0.77
0.61
1098.00
ns, Min
ns, Max
ns, Max
MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2. These items are of interest for Carry Chain applications.
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 54: CLB Distributed RAM Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
Sequential Delays
T_SHCKO
Clock to A – B outputs
T_{SHCKO_1}
Clock to AMUX – BMUX outputs
Setup and Hold Times Before/After Clock CLK
0.92
1.10
1.36
1.49
ns, Max
1.19
1.40
1.71
1.87
ns, Max
T_DS/T_DH
A – D inputs to CLK
0.62/
0.18
0.72/
0.20
0.88/
0.22
0.98/
0.23
ns, Min
T_AS/T_AH
Address An inputs to clock
0.19/
0.52
0.22/
0.59
0.27/
0.66
0.30/
0.75
ns, Min
T_WS/T_WH
WE input to clock
0.27/
0.00
0.32/
0.00
0.40/
0.00
0.47/
–0.03
ns, Min
T_CECK/T_CKCE
CE input to CLK
0.28/
–0.01
0.34/
–0.01
0.41/
–0.01
0.48/
–0.05
ns, Min
Clock CLK
T_MPW
T_MCP
Minimum pulse width
Minimum clock period
0.70
0.82
1.00
1.04
ns, Min
1.40
1.64
2.00
2.08
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2. T_SHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
37