DS152 Datasheet, PDF (40/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 56: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
T_{RCCK_WE}/T_{RCKC_WE}
Write Enable (WE) input (Block RAM only) 0.44/
0.19
0.47/
0.25
0.52/
0.35
0.67/
0.24
ns, Min
T_{RCCK_WREN}/T_{RCKC_WREN}
WREN FIFO inputs
0.47/
0.26
0.50/
0.27
0.55/
0.30
0.68/
0.31
ns, Min
T_{RCCK_RDEN}/T_{RCKC_RDEN}
RDEN FIFO inputs
0.46/
0.26
0.50/
0.27
0.55/
0.30
0.67/
0.31
ns, Min
Reset Delays
T_{RCO_FLAGS}
T_{RCCK_RSTREG}/T_{RCKC_RSTREG}
Reset RST to FIFO Flags/Pointers⁽¹⁰⁾
FIFO reset timing⁽¹¹⁾
0.90
0.22/
0.23
0.98
0.24/
0.24
1.10
0.28/
0.26
1.23
0.31/
0.27
ns, Max
ns, Min
Maximum Frequency
F_MAX
Block RAM
(Write First and No Change modes)
600
540
450
340
MHz
Block RAM (Read First mode)
525
475
400
275
MHz
Block RAM (SDP mode)
525
475
400
275
MHz
F_{MAX_CASCADE}
Block RAM Cascade
(Write First and No Change modes)
550
490
400
300
MHz
Block RAM Cascade (Read First mode)
475
425
350
235
MHz
F_{MAX_FIFO}
F_{MAX_ECC}
FIFO in all modes
600
540
450
340
MHz
Block RAM and FIFO in ECC configuration 450
400
325
250
MHz
Notes:
1. TRACE will report all of these parameters as T_{RCKO_DO}.
2. T_{RCKO_DOR} includes T_{RCKO_DOW}, T_{RCKO_DOPR}, and T_{RCKO_DOPW} as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. T_{RCKO_DO} includes T_{RCKO_DOP} as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6. T_{RCKO_FLAGS} includes the following parameters: T_{RCKO_AEMPTY}, T_{RCKO_AFULL}, T_{RCKO_EMPTY}, T_{RCKO_FULL}, T_{RCKO_RDERR}, T_{RCKO_WRERR.}
7. T_{RCKO_POINTERS} includes both T_{RCKO_RDCOUNT} and T_{RCKO_WRCOUNT.}
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is
possible.
9. T_{RCKO_DI} includes both A and B inputs as well as the parity inputs of A and B.
10. T_{RCO_FLAGS} includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
11. The FIFO reset must be asserted for at least three positive clock edges.
DSP48E1 Switching Characteristics
Table 57: DSP48E1 Switching Characteristics
Symbol
Description
Setup and Hold Times of Data/Control Pins to the Input Register Clock
T_{DSPDCK_{A, ACIN; B, BCIN}_{AREG; BREG}}/
T_{DSPCKD_{A, ACIN; B, BCIN}_{AREG; BREG}}
T_{DSPDCK_C_CREG}/T_{DSPCKD_C_CREG}
{A, ACIN, B, BCIN} input to {A, B}
register CLK
C input to C register CLK
T_{DSPDCK_D_DREG}/T_{DSPCKD_D_DREG}
D input to D register CLK
Speed
Units
-3
-2
-1
-1L
0.25/ 0.29/ 0.35/ 0.46/ ns
0.27 0.30 0.34 0.39
0.16/ 0.19/ 0.22/ 0.33/ ns
0.20 0.22 0.24 0.30
0.07/ 0.10/ 0.15/ 0.24/ ns
0.31 0.34 0.39 0.45
DS152 (v2.10) October18, 2010
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