DS152 Datasheet, PDF (48/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Virtex-6 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 64. Values are expressed in nanoseconds unless otherwise noted.
Table 64: Global Clock Input to Output Delay Without MMCM
Symbol
Description
Device
Speed Grade
-3
-2
-1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM.
T_ICKOF
Global Clock input and OUTFF without XC6VLX75T
4.91
5.32
5.88
MMCM
XC6VLX130T
4.89
5.33
6.00
XC6VLX195T
5.02
5.46
6.13
XC6VLX240T
5.02
5.46
6.13
XC6VLX365T
5.30
5.75
6.43
XC6VLX550T
N/A
6.02
6.72
XC6VLX760
N/A
6.26
6.97
XC6VSX315T
5.40
5.85
6.54
XC6VSX475T
N/A
6.01
6.71
XC6VHX250T
5.18
5.63
6.30
XC6VHX255T
5.20
5.66
6.34
XC6VHX380T
5.38
5.84
6.53
XC6VHX565T
N/A
5.85
6.56
Units
-1L
6.02
ns
6.13
ns
6.27
ns
6.27
ns
6.37
ns
6.60
ns
6.87
ns
6.49
ns
6.61
ns
N/A
ns
N/A
ns
N/A
ns
N/A
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
48