DS152 Datasheet, PDF (45/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 58: Configuration Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
-3
-2
-1
-1L
Units
BPI Master Flash Mode Programming Switching
T_BPICCO(2)
ADDR[25:0], RS[1:0], FCS_B, FOE_B,
6
6
6
7
ns
FWE_B outputs valid after CCLK rising
edge at 2.5V
ADDR[25:0], RS[1:0], FCS_B, FOE_B,
6
6
6
7
ns
FWE_B outputs valid after CCLK rising
edge at 1.8V
T_BPIDCC/T_BPICCD
T_INITADDR
Setup/Hold on D[15:0] data input pins
Minimum period of initial ADDR[25:0]
address cycles
4.0/0.0 4.0/0.0 4.0/0.0 5.0/0.0
ns
3
3
3
3
CCLK cycles
SPI Master Flash Mode Programming Switching
T_SPIDCC/T_SPIDCCD
DIN Setup/Hold before/after the rising 3.0/0.0 3.0/0.0 3.0/0.0 3.5/0.0
ns
CCLK edge
T_SPICCM
MOSI clock to out at 2.5V
MOSI clock to out at 1.8V
6
6
6
7
ns
6
6
6
7
ns
T_SPICCFC
FCS_B clock to out at 2.5V
FCS_B clock to out at 1.8V
6
6
6
7
ns
6
6
6
7
ns
T_FSINIT/T_FSINITH
FS[2:0] to INIT_B rising edge Setup and
2
2
2
2
µs
Hold
CCLK Output (Master Modes)
T_MCCKL
T_MCCKH
CCLK Input (Slave Modes)
Master CCLK clock Low time duty cycle 45/55
Master CCLK clock High time duty cycle 45/55
45/55
45/55
45/55
45/55
45/55
45/55
%, Min/Max
%, Min/Max
T_SCCKL
Slave CCLK clock minimum Low time
2.5
2.5
2.5
2.5
T_SCCKH
Slave CCLK clock minimum High time
2.5
2.5
2.5
2.5
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
ns, Min
ns, Min
F_DCK
T_{MMCMDCK_DADDR}/
T_{MMCMCKD_DADDR}
T_{MMCMDCK_DI}/T_{MMCMCKD_DI}
Maximum frequency for DCLK
DADDR Setup/Hold
DI Setup/Hold
200
1.25/
0.00
1.25/
0.00
200
1.40/
0.00
1.40/
0.00
200
1.63/
0.00
1.63/
0.00
200
1.64/
0.00
1.64/
0.00
MHz
ns
ns
T_{MMCMDCK_DEN}/T_{MMCMCKD_DEN} DEN Setup/Hold time
1.25/ 1.40/ 1.63/ 1.64/
ns
0.00
0.00
0.00
0.00
T_{MMCMDCK_DWE}/T_{MMCMCKD_DWE} DWE Setup/Hold time
T_{MMCMCKO_DO}
T_{MMCMCKO_DRDY}
CLK to out of DO⁽³⁾
CLK to out of DRDY
1.25/ 1.40/ 1.63/ 1.64/
ns
0.00
0.00
0.00
0.00
2.60
3.02
3.64
3.68
ns
0.32
0.34
0.38
0.38
ns
Notes:
1. To support longer delays in configuration, use the design solutions described in Virtex-6 FPGA Configuration User Guide.
2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
3. DO will hold until next DRP operation.
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
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