DS152 Datasheet, PDF (14/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 24: GTX Transceiver Receiver Switching Characteristics
Symbol
Description
F_GTXRX
Serial data rate
RX oversampler not enabled
RX oversampler enabled
T_RXELECIDLE
Time for RXELECIDLE to
respond to loss or
restoration of data
RX_OOBVDPP
OOB detect threshold
peak-to-peak
RX_SST
Receiver spread-spectrum
tracking⁽¹⁾
Modulated @ 33 KHz
RX_RL
Run length (CID)
RX_PPMTOL
Data/REFCLK PPM offset
tolerance
SJ Jitter Tolerance⁽²⁾
JT_SJ_6.5
Sinusoidal Jitter⁽³⁾
JT_SJ_5.0
Sinusoidal Jitter⁽³⁾
JT_SJ_4.25
Sinusoidal Jitter⁽³⁾
JT_SJ_3.75
Sinusoidal Jitter⁽³⁾
JT_SJ_3.125
Sinusoidal Jitter⁽³⁾
JT_SJ_3.125L
Sinusoidal Jitter⁽³⁾
JT_SJ_2.5
Sinusoidal Jitter⁽³⁾
JT_SJ_1.25
Sinusoidal Jitter⁽³⁾
JT_SJ₆₀₀
Sinusoidal Jitter⁽³⁾
JT_SJ₄₈₀
Sinusoidal Jitter⁽³⁾
SJ Jitter Tolerance with Stressed Eye⁽²⁾
Internal AC capacitor bypassed
CDR 2^nd-order loop disabled
CDR 2^nd-order loop enabled
6.5 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.125 Gb/s
3.125 Gb/s⁽⁴⁾
2.5 Gb/s⁽⁵⁾
1.25 Gb/s⁽⁶⁾
600 Mb/s
480 Mb/s
JT_TJSE_3.125
Total Jitter with Stressed
Eye⁽⁷⁾
3.125 Gb/s
5.0 Gb/s
JT_SJSE_3.125
Sinusoidal Jitter with
Stressed Eye⁽⁷⁾
3.125 Gb/s
5.0 Gb/s
Notes:
1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 1e^–12.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. PLL frequency at 1.5625 GHz and OUTDIV = 1.
5. PLL frequency at 2.5 GHz and OUTDIV = 2.
6. PLL frequency at 2.5 GHz and OUTDIV = 4.
7. Composite jitter with RX equalizer enabled. DFE disabled.
Min
0.600
0.480
–
Typ
Max Units
–
F_GTXMAX Gb/s
–
0.600 Gb/s
75
–
ns
60
–
–5000
–
–
–
–200
–
–2000
–
0.44
–
0.44
–
0.44
–
0.44
–
0.45
–
0.45
–
0.5
–
0.5
–
0.4
–
0.4
–
0.70
–
0.70
–
0.1
–
0.1
–
150
mV
0
ppm
512
UI
200
ppm
2000 ppm
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
14