DS152 Datasheet, PDF (20/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 37: GTH Transceiver Receiver Switching Characteristics
Symbol
Description
R_XRL
Run length (CID)
R_XPPMTOL
Data/REFCLK PPM offset tolerance
SJ Jitter Tolerance^(1)(2)(3)
JT_SJ_11.18
JT_SJ_10.32
JT_SJ_9.95
JT_SJ_2.667
JT_SJ_2.48
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
11.18 Gb/s
10.32 Gb/s
9.95 Gb/s
2.667 Gb/s
2.48 Gb/s
Notes:
1. These values are NOT intended for protocol specific compliance determinations.
2. All jitter values are based on a bit error ratio of 1e^–12.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
Min
Typ
–200
Ethernet MAC Switching Characteristics
Consult Virtex-6 FPGA Embedded Tri-mode Ethernet MAC User Guide for further information.
Table 38: Maximum Ethernet MAC Performance
Symbol
Description
Conditions
F_TEMACCLIENT Client interface maximum
frequency
F_TEMACPHY
Physical interface maximum
frequency
10 Mb/s – 8-bit width
100 Mb/s – 8-bit width
1000 Mb/s – 8-bit width
1000 Mb/s – 16-bit width
2000 Mb/s – 16-bit width
2500 Mb/s – 16-bit width
10 Mb/s – 4-bit width
100 Mb/s – 4-bit width
1000 Mb/s – 8-bit width
2000 Mb/s – 8-bit width
2500 Mb/s – 8-bit width
-3
2.5⁽¹⁾
25⁽²⁾
125
62.5
125
156.25
2.5
25
125
250
312.5
Speed Grade
-2
-1
2.5⁽¹⁾
25⁽²⁾
2.5⁽¹⁾
25⁽²⁾
125
125
62.5
62.5
125
125
156.25 156.25
2.5
2.5
25
25
125
125
250
250
312.5 312.5
Notes:
1. When not using clock enable, the F_MAX is lowered to 1.25 MHz.
2. When not using clock enable, the F_MAX is lowered to 12.5 MHz.
Max Units
UI
200
ppm
UI
UI
UI
UI
UI
-1L
2.5⁽¹⁾
25⁽²⁾
125
62.5
N/A
N/A
2.5
25
125
N/A
N/A
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
20