DS152 Datasheet, PDF (30/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4" trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure 6 and Figure 7.
X-Ref Target - Figure 6
V_REF
FPGA Output
R_REF
V_MEAS
(voltage level when taking
delay measurement)
C_REF
(probe capacitance)
ds152_06_042109
Figure 6: Single Ended Test Setup
X-Ref Target - Figure 7
FPGA Output
+
C_REF
R_REF V_MEAS
–
ds152_07_042109
Figure 7: Differential Test Setup
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters V_REF, R_REF, C_REF, and V_MEAS fully describe
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
1. Simulate the output driver of choice into the generalized
test setup, using values from Table 47.
2. Record the time to V_MEAS.
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4. Record the time to V_MEAS.
5. Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
Table 47: Output Delay Measurement Methodology
Description
I/O Standard
Attribute
R_REF C_REF⁽¹⁾ V_MEAS V_REF
(Ω) (pF)
(V) (V)
LVCMOS, 2.5V
LVCMOS25
1M
0
1.25
0
LVCMOS, 1.8V
LVCMOS18
1M
0
0.9
0
LVCMOS, 1.5V
LVCMOS15
1M
0
0.75
0
LVCMOS, 1.2V
LVCMOS12
1M
0
0.75
0
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL_I
HSTL_II
HSTL_III
50
0
V_REF 0.75
25
0
V_REF 0.75
50
0
0.9
1.5
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL_I_18
HSTL_II_18
HSTL_III_18
50
0
V_REF
0.9
25
0
V_REF
0.9
50
0
1.1
1.8
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
BLVDS (Bus LVDS), 2.5V
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
LVDS_25
LVDS_25
BLVDS_25
50
0
25
0
50
0
25
0
100
0
100
0
100
0
V_REF
V_REF
V_REF
V_REF
0⁽²⁾
0⁽²⁾
0⁽²⁾
0.9
0.9
1.25
1.25
1.2
1.2
0
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
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