DS152 Datasheet, PDF (13/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 23: GTX Transceiver Transmitter Switching Characteristics
Symbol
Description
Condition
Min
Typ
Max Units
F_GTXTX
T_RTX
T_FTX
T_LLSKEW
V_TXOOBVDPP
T_{TXOOBTRANSITION}
TJ_6.5
DJ_6.5
TJ_5.0
DJ_5.0
TJ_4.25
DJ_4.25
TJ_3.75
DJ_3.75
TJ_3.125
DJ_3.125
TJ_3.125L
DJ_3.125L
TJ_2.5
DJ_2.5
TJ_1.25
DJ_1.25
TJ₆₀₀
DJ₆₀₀
TJ₄₈₀
DJ₄₈₀
Serial data rate range
TX Rise time
TX Fall time
TX lane-to-lane skew⁽¹⁾
Electrical idle amplitude
Electrical idle transition time
Total Jitter⁽²⁾⁽³⁾
Deterministic Jitter⁽²⁾⁽³⁾
Total Jitter⁽²⁾⁽³⁾
Deterministic Jitter⁽²⁾⁽³⁾
Total Jitter⁽²⁾⁽³⁾
Deterministic Jitter⁽²⁾⁽³⁾
Total Jitter⁽²⁾⁽³⁾
Deterministic Jitter⁽²⁾⁽³⁾
Total Jitter⁽²⁾⁽³⁾
Deterministic Jitter⁽²⁾⁽³⁾
Total Jitter⁽²⁾⁽³⁾
Deterministic Jitter⁽²⁾⁽³⁾
Total Jitter⁽²⁾⁽³⁾
Deterministic Jitter⁽²⁾⁽³⁾
Total Jitter⁽²⁾⁽³⁾
Deterministic Jitter⁽²⁾⁽³⁾
Total Jitter⁽²⁾⁽³⁾
Deterministic Jitter⁽²⁾⁽³⁾
Total Jitter⁽²⁾⁽³⁾
Deterministic Jitter⁽²⁾⁽³⁾
20%–80%
80%–20%
6.5 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.125 Gb/s
3.125 Gb/s⁽⁴⁾
2.5 Gb/s⁽⁵⁾
1.25 Gb/s⁽⁶⁾
600 Mb/s
480 Mb/s
0.480
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
F_GTXMAX Gb/s
120
–
ps
120
–
ps
–
350
ps
–
15
mV
–
75
ns
–
0.33
UI
–
0.17
UI
–
0.33
UI
–
0.15
UI
–
0.33
UI
–
0.14
UI
–
0.34
UI
–
0.16
UI
–
0.2
UI
–
0.1
UI
–
0.35
UI
–
0.16
UI
–
0.20
UI
–
0.08
UI
–
0.15
UI
–
0.06
UI
–
0.1
UI
–
0.03
UI
–
0.1
UI
–
0.03
UI
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to 12 consecutive transmitters (three fully populated GTX Quads).
2. Using PLL_DIVSEL_FB = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
3. All jitter values are based on a bit-error ratio of 1e^-12.
4. PLL frequency at 1.5625 GHz and OUTDIV = 1.
5. PLL frequency at 2.5 GHz and OUTDIV = 2.
6. PLL frequency at 2.5 GHz and OUTDIV = 4.
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
13