DS152 Datasheet, PDF (41/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 57: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
-3
Setup and Hold Times of Data Pins to the Pipeline Register Clock
T_{DSPDCK_{A, ACIN, B, BCIN}_MREG_MULT}/
T_{DSPCKD_{A, ACIN, B, BCIN}_MREG_MULT}
T_{DSPDCK_{A, D}_ADREG}/ T_{DSPCKD_{A, D}_ADREG}
{A, ACIN, B, BCIN} input to M register
CLK
{A, D} input to AD register CLK
2.36/
0.04
1.24/
0.10
Setup and Hold Times of Data/Control Pins to the Output Register Clock
T_{DSPDCK_{A, ACIN, B, BCIN}_PREG_MULT}/
T_{DSPCKD_{A, ACIN, B, BCIN}_PREG_MULT}
T_{DSPDCK_D_PREG_MULT}/
T_{DSPCKD_D_PREG_MULT}
T_{DSPDCK_{A, ACIN, B, BCIN}_PREG}/
T_{DSPCKD_{A, ACIN, B, BCIN}_PREG}
T_{DSPDCK_C_PREG}/ T_{DSPCKD_C_PREG}
{A, ACIN, B, BCIN} input to P register
CLK using multiplier
D input to P register CLK
{A, ACIN, B, BCIN} input to P register
CLK not using multiplier
C input to P register CLK
3.83/
–0.13
3.62/
–0.47
1.59/
–0.13
1.42/
–0.10
T_{DSPDCK_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG}/ {PCIN, CARRYCASCIN, MULTSIGNIN} 1.23/
T_{DSPCKD_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG} input to P register CLK
–0.02
Setup and Hold Times of the CE Pins
T_{DSPDCK_{CEA; CEB}_{AREG; BREG}}/
T_{DSPCKD_{CEA; CEB}_{AREG; BREG}}
T_{DSPDCK_CEC_CREG}/ T_{DSPCKD_CEC_CREG}
{CEA; CEB} input to {A; B} register CLK 0.14/
0.19
CEC input to C register CLK
0.15/
0.18
T_{DSPDCK_CED_DREG}/ T_{DSPCKD_CED_DREG}
CED input to D register CLK
0.20/
0.12
T_{DSPDCK_CEM_MREG}/ T_{DSPCKD_CEM_MREG}
CEM input to M register CLK
0.16/
0.19
T_{DSPDCK_CEP_PREG}/ T_{DSPCKD_CEP_PREG}
CEP input to P register CLK
0.32/
0.02
Setup and Hold Times of the RST Pins
T_{DSPDCK_{RSTA; RSTB}_{AREG; BREG}}/
T_{DSPCKD_{RSTA; RSTB}_{AREG; BREG}}
T_{DSPDCK_RSTC_CREG}/ T_{DSPCKD_RSTC_CREG}
{RSTA, RSTB} input to {A, B} register
CLK
RSTC input to C register CLK
0.27/
0.17
0.18/
0.08
T_{DSPDCK_RSTD_DREG}/ T_{DSPCKD_RSTD_DREG} RSTD input to D register CLK
0.28/
0.15
T_{DSPDCK_RSTM_MREG}/ T_{DSPCKD_RSTM_MREG} RSTM input to M register CLK
0.20/
0.24
T_{DSPDCK_RSTP_PREG}/ T_{DSPCKD_RSTP_PREG} RSTP input to P register CLK
0.26/
0.04
Combinatorial Delays from Input Pins to Output Pins
T_{DSPDO_{A, B}_{P, CARRYOUT}_MULT}
{A, B} input to {P, CARRYOUT} output 3.76
using multiplier
T_{DSPDO_D_{P, CARRYOUT}_MULT}
D input to {P, CARRYOUT} output using 3.57
multiplier
T_{DSPDO_{A, B}_{P, CARRYOUT}}
{A, B} input to {P, CARRYOUT} output 1.55
not using multiplier
T_{DSPDO_{C, CARRYIN}_{P, CARRYOUT}}
{C, CARRYIN} input to {P, CARRYOUT} 1.38
output
Speed
-2
-1
2.70/
0.04
1.42/
0.12
3.21/
0.04
1.69/
0.13
4.37/ 5.20/
–0.13 –0.13
4.13/ 4.90/
–0.47 –0.47
1.81/ 2.15/
–0.13 –0.13
1.61/
–0.10
1.41/
–0.02
1.91/
–0.10
1.67/
–0.02
0.17/
0.22
0.18/
0.20
0.24/
0.13
0.20/
0.21
0.38/
0.02
0.22/
0.25
0.24/
0.23
0.31/
0.14
0.26/
0.25
0.46/
0.03
0.31/
0.19
0.20/
0.08
0.32/
0.16
0.23/
0.26
0.30/
0.04
0.38/
0.22
0.23/
0.09
0.38/
0.19
0.26/
0.30
0.35/
0.05
4.29 5.08
4.07 4.82
1.76 2.07
1.56 1.83
-1L
3.66/
0.02
1.91/
0.16
5.94/
–0.24
5.61/
–0.77
2.44/
–0.24
2.16/
–0.19
1.91/
–0.07
0.30/
0.28
0.31/
0.26
0.43/
0.16
0.32/
0.28
0.54/
0.04
0.41/
0.25
0.27/
0.11
0.45/
0.21
0.29/
0.34
0.43/
0.06
5.87
5.57
2.41
2.13
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
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